| Per Westermark 06/21/09 23:55 Read: 241 times Sweden |
#166324 - volatile + racing condition Responding to: Murray R. Van Luyn's previous message |
Just a quick note.
Variables shared between an ISR and the main application should be specified volatile, to order the compiler to not cache them. Another thing - the timer variables are larger than one byte which means that an 8-bit processor is not guaranteed to read them atomically. This can lead to problems when the ISR is decrementing them while you at the same time test if any of them is expired. If the variable has the value 0x0100, the compiler could pick up the low byte and see that it is zero. Then the ISR could come in and decrement the value to 0x00ff. After the ISR, the generated code could pick up the high byte and check if this one is zero. So depending on which byte order the compiler selects when checking for zero, the application could time out a timer with 255 ticks left. Another thing here is that since you count down to zero and then assign new values - and turn off the reload interrupt when updating a timer - this solution will not allow the creation of a loop that runs at a fixed frequency. There is always the possibility of a slow time creep, where a 100ms delay may actually become 100, 100, 101, 100, 101, 100, 101, ... On one hand, I prefer a solution that never ever stops the timer ISR. On the other hand, timers are scarce, so I think you should do more with your ISR. At the very least, you should let the ISR increment a global "uptime" variable every ms. Possibly also a 1s variable every 1000 interrupts. This would allow your main loop to create long (and exact) delays or to keep track of time. |
| Topic | Author | Date |
| Pseudo timers make programming delays easy. | Murray R. Van Luyn | 06/21/09 23:10 |
| volatile + racing condition | Per Westermark | 06/21/09 23:55 |
| slow processors | Per Westermark | 06/22/09 01:27 |
| You beat me to it... | Jez Smith | 06/22/09 01:50 |
| Timers_0.1 available. | Murray R. Van Luyn | 06/22/09 01:52 |
| SDCC | Jan Waclawek | 06/22/09 02:19 |
| ISR defining with SDCC | Mahesh Joshi | 06/22/09 02:42 |
| oh, I just read it in the manual | Jan Waclawek | 06/22/09 02:50 |
| only conditionally, as #ifdef SDCC | Andy Neil | 06/22/09 03:20 |
| SDCC and ISRs | Andy Peters | 06/23/09 14:17 |
| Prototyping ISRs | Andy Neil | 06/23/09 16:04 |
| you can see it as if.... | Jan Waclawek | 06/23/09 16:39 |
| SDCC Quirk? | Andy Neil | 06/23/09 16:56 |
internals of SDCC | Maarten Brock | 07/08/09 14:31 |
| duh | Andy Peters | 06/24/09 14:49 |
| Too quick | Per Westermark | 06/22/09 02:38 |
| I see something else... | Jan Waclawek | 06/22/09 02:53 |
| That helped. | Murray R. Van Luyn | 06/22/09 22:33 |
| Oops! Timers_0.2 available. | Murray R. Van Luyn | 06/22/09 22:23 |
| you persist | Erik Malund | 06/23/09 07:25 |
| Good idea! | Andy Neil | 06/22/09 01:46 |
| atomicity | Erik Malund | 06/22/09 08:13 |
| No | Jez Smith | 06/23/09 08:40 |
| I gladly, click on a link .... | Erik Malund | 06/23/09 08:53 |
| Direct link | Jon Ledbetter | 06/23/09 10:54 |
| that was clearly possible, I wonder why ... | Erik Malund | 06/23/09 14:11 |
| one more thing, now we are digging deep | Erik Malund | 06/25/09 06:37 |



