Per:
I do agree with your points about PCI bus performance bottle necking. That can really be a problem when maximum I/O device throughput becomes a significant part of bus speeds and when multiple devices share the same data paths. But this problem is not new with PCI. There have always been classes of applications that have been affected by these issues. I could list a whole series of problems like this that relate to designs from the first 8085's/Z80s up to the modern multi-core CPUs with fancy new high performance buses. In all cases it is the issue of applicability of the architecture and its performance to the would be application scenarios.

A good specific example is to take a look at a modern PC and see that 10 or 12 motherboard hosted USB2.0 high speed ports will likely not sustain any where near the 480Mbit data transfer rate on a single port when multiple devices are connected and in parallel usage.

I just really need to point out that finding compatibility and usage model functionality for parallel port adapters is really a separate subject from data transfer performance. The I/O device availability and data flow rate will come into play after one has found a usable connection path to match the I/O device and software in use.

Michael Karas