Tutorial: Introduction to Flash Memory NOTE: This document was contributed to 8052.com by Waferscale, a manufacturer of Flash Memory devices that work with the 8052 architecture. Introduction Today, more than ever, consumers are demanding electronic products that include more features, but they're not willing to pay the added costs to get them. Many embedded systems programmers are now using high-level languages, requiring large amounts of memory for program store. As a result, designers are taking advantage of declining costs and increased densities of Flash memory to compete. It would be all too easy if a designer could simply replace PROM or EPROM with flash memory and move on, but it's not that simple. Having flash memory is only part of the solution. Being able to program flash memory after it is soldered into a product is essential. Here are just a few benefits derived from a system with flash memory that is capable of In-System Programming (ISP): Time to develop code is reduced Products can be tested and tailored at the end of the assembly line Code bugs can be corrected in the field New product features can be added easily, even remotely All of this is possible without dismantling the end product (too bad the US Postal Service couldnt ISP their postage stamp vending machines after the $20 bill was refaced). This tutorial presents the issues associated with ISP flash designs, general methods to implement ISP, and a how to implement ISP Flash in an embedded 8051 design. How much flash memory is enough? Firmware often outgrows the memory capacity originally designed into a system. This is most likely to occur when the systems differentiating features are embodied in the firmware, or when the code is written in a high-level language that requires an OS kernel. As a result, 64K bytes of flash memory are a bare minimum for many of todays embedded 8-bit CISC designs. Since flash is electrically erasable and programmable, one also has to consider the amount of flash memory needed for data storage and recording. These features can greatly enhance a products marketability. Flash memory used for data now becomes a partitioning nightmare for MCUs with separate program and data space, such as the 8051. ISP is not as easy as it seems An embedded system capable of ISP means that a host computer can download firmware into flash memory through a communications channel. Although the channel of choice is typically a UART, it can be any communication channel that the MCU supports (Ethernet, J1850, CAN, HPIB, etc). As easy as this seems, there is a fundamental problem. You can't erase or write to the same flash memory from which you are executing code. If the MCUs boot code and programming algorithms (ISP loader code) are stored in this flash memory, they will be unavailable to the MCU during ISP. Therefore, it is nearly impossible to implement ISP of flash memory under MCU control in an embedded system that contains only a single flash memory. It is absolutely necessary to use an additional independent memory to execute the ISC loader code. Difficulties of the 8051 MCU and ISP The 8051 architecture provides two separate address spaces, one for program memory and one for data memory. These MCUs are specifically designed such that they will NOT write to program space under any circumstance. Although this inherent inability to write to program space prevents program code from being overwritten by data, it makes MCU-controlled in-system programming impossible unless the system is "tricked". One way to trick the system is to temporarily "reclassify" flash memory as data space instead of program space during ISP, then back to program space when ISP is complete. The system implications are complex, but possible. Another way is to externally combine flash memory into both program space and data space, but this eliminates the protection offered by separate spaces and reduces the total address space by a factor of two. In addition, the 8051 provides a maximum of 64K bytes of linear address space, which, as previously mentioned, falls short for many systems' memory requirements of today. It is because of this that paging (or banking) becomes a necessity. Paging is not a new concept, but can get complicated when an already crowded memory map must now accommodate temporary ISP loader code. You must now provide the means to dynamically swap ISP loader code into and out of the active memory map to optimize this tight address space. Programmable logic is perfect for this operation. Jumping the Hurdles There are major challenges that designers face when implementing ISP with external flash, which are: Building the MCU-to-flash interface Adding a second memory array from which the MCU can operate during ISP Overcoming the inability of 8051 MCUs to write to program memory. Designing the MCU interface and adding a second memory array for ISP are related in that they can be affected by the level of integration of the flash memory device. A typical discrete solution will include a flash device, a second memory array for ISP, address latches, and a CPLD for address decoding, control logic and implementation of paging/segmentation schemes to enable ISP. The choice of the second memory array depends on the design requirements. Using an SRAM for the second memory array offers the ability to update the boot and programming algorithms in addition to the application firmware. However, extra measures must be taken to recover from an interruption of power during ISP, which could render the system dysfunctional. While a separate ROM is the most stable and least expensive solution, it precludes any updates to the boot code or programming algorithms. The best choice is an EEPROM or second flash memory, as this ensures the integrity of the boot code and programming algorithms in the event of a power loss during ISP, while, at the same time offers the option of updating the boot code. Finally, there are a number of highly integrated flash devices available today that integrate several memory arrays on a single substrate that can operate concurrently (read from one while writing to another). This is the ideal architecture for implementing ISP. The option that is right for you will be dictated by cost, power and PC board real-estate considerations. The addition of external devices can result in a disproportionate increase in board size and power consumption. Figure 1 shows the block diagram of a discrete solution, which connects a flash memory, an SRAM, and an EEPROM to an 8052 based microcontroller. This design offers ample flash memory for program and/or data space. It also provides SRAM and EEPROM that can be used for code (boot loader or other) and data storage. To take full advantage of these memories, some programmable logic is needed. A 64 Macrocell CPLD is employed to decode memory and I/O addresses, implement memory segmentation and paging, provide dynamic swapping of segments, and manipulate program and data space during ISP. The CPLD also replaces the I/O ports lost due to external address and data signals required by the 8051. Note that while the flash and EEPROM can be programmed in-system through the UART, the CPLD cannot. Figure 1. Discrete Flash 8051 Design Implementation In contrast, a highly integrated two-chip solution as shown in Figure 2 is implemented with Waferscales EasyFLASH PSD813F1. While it may be marginally more expensive than a system implemented with discrete devices, it provides several benefits over the discrete solution: Two independent memory arrays (128Kx8 flash and 32Kx8 EEPROM) that can operate concurrently. The EEPROM can be divided up so that part of it is used to hold ISP loader code, leaving the remainder for use as data memory. A third independent memory array, 2Kx8 SRAM. All ISP issues regarding program vs. data space, memory paging, and memory swapping are taken care of by the by the device at the silicon level. Internal control registers and logic provide memory segmenting, paging, swapping, and dynamic management of program and data space. The entire device may be programmed and configured with the IEEE-1149.1 JTAG channel at any time without MCU participation, even when the device is completely blank. Memories are built on zero-power technology, which means they draw only standby current between MCU accesses and very low current at other times. The entire device erases and programs at a single VCC level (no VPP needed), and the flash memory is good for at least 100,000 cycles. Programmable memory decoder logic. General purpose programmable CPLD for user specific logic. Programmable I/O. A security bit protects all memory and configuration from undesired viewing. Figure 2. Highly Integrated Flash 8051 Design with Waferscale's PSD813F1 Waferscale offers five varieties of the PSD813F family, all members include the basic features: JTAG ISP, programmable logic, additional I/O, low-power silicon techniques, and memory security. However, each family member offers a different combination of concurrent, independent memories within the device. PSD813F1: 128K bytes flash, 32K bytes EEPROM, 2K bytes SRAM PSD813F2: 128K bytes flash, 32K bytes flash, 2K bytes SRAM PSD813F3: 128K bytes flash, 2K bytes SRAM PSD813F4: 128K bytes flash, 32K bytes flash PSD813F5: 128K bytes flash Choose the PSD to best optimize your design. System design for these PSD devices is simplified with PSDsoft, Waferscales software development tool. Device configuration of the PSD is entered in a simple point-and-click fashion, the programmable logic is described using Abel (HDL), and the MCU firmware is easily merged with the PSD design to produce one programmable file. Any 8051 compiler/linker can be used as long as it outputs a file in the Intel Hex format. PSDsoft will program a PSD device using either a serial JTAG cable or a standalone device programmer. PSDsoft directly supports the low-cost FlashLink JTAG ISP cable or the PSDpro device programmer. Both of these programmers from Waferscale connect to the PCs parallel port. Third party programmers may also be used. Conclusion To satisfy the memory requirements of many of todays embedded 8051 based applications and take full advantage of the characteristics of flash memory, one must consider the impact of cost, size, power, flexibility, time-to-market, security, and manufacturing when choosing an implementation. A combination of an 8051 based microcontroller with the Waferscale PSD813F family of ISP flash devices is well suited to satisfy all of these issues. For more information, including PSD813F data sheets and application notes, please visit http://www.st.com. (C) Copyright 1997 - 2008 by Vault Information Services LLC. All Rights Reserved. Information provided "as-is" without warranty. Please see details. Contact us for usage and copy permission.